Dynamic Random Access Memory (DRAM) fail bit counts are expected to increase significantly as DRAM technology approaches its scaling limit (˜10 nm nodes). The more fail bit counts increase, the less stable memory system become and system backup solutions to prevent this fatal problem are required.
DRAM specifications define post package repair (PPR) to repair the small number of fails that occur during package assembly. This specification assumes the DRAM receives the fail address captured by a tester during the final test of the DRAM after assembly. However, this scheme does not provide the solutions to fix the random errors that occur at the system level during operation.
Accordingly, there are long-felt industry needs for methods that improve upon conventional methods including the improved methods and apparatus provided hereby.
The inventive features that are characteristic of the teachings, together with further features and advantages, are better understood from the detailed description and the accompanying figures. Each of the figures is provided for the purpose of illustration and description only, and does not limit the present teachings.